| 摘要 |
PURPOSE:To improve performance, and to enhance the degree of integration by forming two pairs of semiconductor regions and first, second and third impurity regions to the same semiconductor substrate and connecting the two pairs in series between power terminals. CONSTITUTION:An N-type well region 402 and an N-type source region 403 and a drain and base common N-type region 501 in a NMOS and P-N-P common element 102 are shaped to a P-type substrate 401. A P-type source region 406 and a drain and base common P-type region 502 in a PMOS and N-P-N common element 101 are formed into the N-type well region. An N-type emitter region 410 is shaped into the P-type region 502 and a P-type emitter region 409 into the N-type region 501. The NMOS and P-N-P common element 102 and the PMOS and N-P-N common element 101 are parted by a thick oxide film 411, and each element is formed in one element form. A gate oxide film 412 is shaped to the surface, and polysilicon gate electrodes 413 for MOS transistors are formed. |
