| 摘要 |
PCT No. PCT/SE86/00091 Sec. 371 Date Oct. 30, 1986 Sec. 102(e) Date Oct. 30, 1986 PCT Filed Mar. 4, 1986 PCT Pub. No. WO86/05321 PCT Pub. Date Sep. 12, 1986.A method for manufacturing integrated circuits in which conductors and gate structures are built-up on a substrate plate, the conductors incorporating a layer of polycrystalline silicon and the gate structures including a gate electrode of polycrystalline silicon, where each of the gate structures is surrounded by doped source-and-drain-areas and where the gate electrode and the source-and-drain-areas respectively are metallized by depositing thereon a metal which reacts with the silicon from which the gate electrode and the source-and-drain-areas are comprised, so as to form a silicide layer. In accordance with the invention the gate electrode (3) is metallized in a first process stage. The source-and-drain-areas (18, 19) are metallized in a later process stage. Subsequent to metallizing the gate electrode in the first process stage, a protective layer (5) is applied to the metallized layer (4) of the gate electrode in a second process stage. All layers (16, 13, 7) present on the source-and-drain-areas (18, 19) are then removed to expose silicon, whereafter a metal (8) capable of reacting with the exposed silicon is deposited over the substrate, therewith to metallize (9, 10) the source-and-drain-areas (18, 19). In the second process stage, the protective layer (5) is given a thickness such that subsequent to the aforementioned etching process there remains a given, smallest thickness sufficient to ensure that the deposited metal (8) will not react with the silicon of the gate electrode (3, 4).
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