发明名称 |
Up/down counter device with reduced number of discrete circuit elements |
摘要 |
An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit. The output of the first logic circuit section of each of the first to the n-th logic circuits is connected to the input of the first logic circuit section of the post stage logic circuit.
|
申请公布号 |
US4741006(A) |
申请公布日期 |
1988.04.26 |
申请号 |
US19850754398 |
申请日期 |
1985.07.12 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
YAMAGUCHI, AKIRA;SATOH, KOICHI;ISEKI, HIDEMI;SHIGEHARA, HIROSHI |
分类号 |
H03K23/56;(IPC1-7):H03K23/00;H03K23/04 |
主分类号 |
H03K23/56 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|