| 摘要 |
PURPOSE:To attain both small power consumption and high-speed working in a programmable logic circuit device by providing selectively a bipolar element to an active circuit of an input/output part and using the CMOS elements to form other internal active circuits among those circuits constituting a programmable logic circuit PLD. CONSTITUTION:A PLD100 contains an input buffer circuit G1 and an output buffer circuit G5 which have bipolar transistors at the output stages and the CMOS (complementary) TR at the preceding stages respectively. In other words, the PLD100 consists of a bipolar/CMOS composite logic circuit. While other internal active circuits, e.g., a multi-input AND gate G3 consists of CMOS circuit only. Furthermore an exclusive OR gate G4 serving as the load of the G3 is also provided with a CMOS circuit only. Thus it is possible to transmit the satisfactorily fast signals even by an extremely small drive capacity within a range between the output side of an OR array 1 and the input side of a tri state output buffer G5. |
