| 摘要 |
PURPOSE:To leave a part of data to be transferred to a transfer opposite at need, by deciding write on a memory area by priority. CONSTITUTION:Transfer priority (i-bits) that is a part of a transfer instruction from a CPU is set at a priority register 22 from an external bus 11 through a command controller. The priority from the memory of a transfer destination address is read in a priority buffer 20 through a priority bus 15, and is compared with the content of the priority register 22 at a comparator 21. A timing controller 26 generates a write enable signal only when a compared result that the priority from the memory is smaller than a transferred priority, is obtained, and permits the write on the memory. In this way, it is possible to leave a part of the data in the memory at time of transfer, or a transfer area in an input/output device, at time of DMA transfer, as it is, at need. |
