| 摘要 |
PURPOSE:To reduce the cell-layout area of an N-MOS drawing-out type Bipolar- C-MOS logic circuit by a method wherein N-MOS FET's which draw out base charges of bipolar transistors are piled into three-layers and the gates of them are so arranged as to be pierced by straight lines. CONSTITUTION:The semiconductor device is composed of diffused layers 101, polycrystalline silicon layers 102, first metal layers 103 and contact holes 105 connecting the polycrystalline silicon layers or the diffused layers to the first metal layers. The respective input signals 11-14 pass through rows 1-3 of MOS FET's with straight lines. An N-MOS FET 4 which draws out the base charge of a bipolar transistor 6 to which an N-MOS FET is connected has a diffused layer in common with an N-MOS FET 2 constituting a logic and is arranged adjacent to the N-MOS FET 2. Electric source 20 and a ground 30 are passing through the upper and lower sides of the cells in the first metal layer respectively along the horizontal direction. If the number of metal layers is not limited to one like this and 2nd metal layer can be used in the cell layout, the cell layout area can be further reduced. |
