| 摘要 |
PURPOSE:To stably count an n-notation number independently of the clock pulse frequency by loading a setting value to a counter synchronously with the clock pulse in response to it that a down-counter outputs a carry signal in the n-notation counter counting the clock pulser of the n-notation number. CONSTITUTION:When a clock pulse CP is led to an H level, a NAND gate 6 outputs a SET' signal going to an L level by a 1/2 clock period only. A setting value '2' set by a setting section 2 is loaded to a down-counter 1 by the SET' signal. When the clock pulse CP is descended to the L level, as soon as the output of the NAND gate 6 goes to the H level, a flip-flop 5 is reset. When the down-counter 1 counts down sequentially from the count '2' and the count reaches '0', an ncp signal is outputted and the flip-flop 5 is set. Thus, the setting value of the setting section 2 is loaded stably to the down counter 1 independently of the frequency of the clock pulse CP.
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