| 摘要 |
PURPOSE:To facilitate integration and the same time to realizea logical shift by carrying out the right and left shifts along a single route by means of a shifter array and providing a precharging circuit to each input/output terminal to perform the data processing in an inverted logic. CONSTITUTION:A PMOS transistor 13 is turned on while a clock phi is kept at H before shift and an input/output terminal 16 is precharged. In a left shift mode the data received via an input bus 4 is inputted from a data input terminal 6 of a register 1 via a transmission gate 7. Then the terminal 16 is set at L if the data is set at H when an output control signal C4 is set at H. While the precharged value H is held on the terminal 16 if the data is kept at L. The output data is inputted from the terminal 16 of a register 2 through a shifter array 3 and inverted by an inverter 12 to be written to the register 2 through a transmission gate 8. The data shift and stored in the register 2 is outputted to an output bus 5 from a tri-state buffer 18. |
