Phase-locked loop

摘要

To recover a clock from a signal which is present at a first input (1) of the phase discriminator (2) in a phase-locked loop (PLL) with phase discriminator (2) and voltage-controlled oscillator (6) but without integrator, a multi-stage phase shifter (12) and a change-over switch (13) are arranged between the output of the voltage-controlled oscillator (6) and the second input (11) of the phase discriminator (2) in such a manner that any stage output of the phase shifter (12) can be applied to the second input (11) of the phase discriminator (2). A control logic (14) measures the phase difference between the first input (1) of the phase shifter (2) and one of the outputs of the phase shifter (12) and selects a switch position of the change-over switch (13). This makes it possible to keep the phase differences low even in an integrated circuit without analog integrator. This is of particular advantage in the recovery of a plesiochronous clock in a demultiplexer. <IMAGE>