| 摘要 |
Data blocks which have m positions and which are made up of p data words each with n positions are received into and read out of the memory array (s). The data words appear on the input buses (be1 ... bex) of the memory arrangement in the cycle of the system clock (t) and are output again on its output buses (ba1 ... bax). The individual data words are assigned to and ordered in the data blocks using the input connection matrix (ek), under control of the setup signals (e1, e2), which are calculated and derived from the setup data (ed) using the microprocessor (mp) and the intermediate memory (rm). Thus any required assignment of inputs and outputs is possible. The memory arrangement is particularly suitable for storage of video signals. Different recording methods (RGB, YUV, composite colour video, etc.) are possible, also with different data rates of the individual channels.
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