| 摘要 |
An arrangement for conversion of virtual addresses into physical addresses in a data processing system, using an address translation memory. The address translation memory contains a segment table address register, a register for the virtual addresses, a working memory subdivision register, which subdivides the working memory into a user part and a system part, a comparator which is assigned to the working memory subdivision register, a working memory address register, and control logic. An ATM memory, which is connected indirectly via a comparator unit to the control logic, is provided. A circuit arrangement consisting of an associative memory (ASS) with an associated control unit (ASS-ST), with a multiplexer (MUX) connected in series, is inserted between the segment table address register (STAR) and the ATM memory (ATM-MEM). The multiplexer (MUX) has two signal inputs, one signal output and one signal input. A signal (VADR SYP), which indicates whether a given address is a system address or a user address, can be fed to the control input of the comparator (K) which is assigned to the register for the virtual addresses (VADR). <IMAGE>
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