发明名称 CONTINUOUS VARIABLE MODE PLL CIRCUIT
摘要 PURPOSE:To more precisely cope with the lock state by applying a phase lock signal from a phase comparator to a terminal, which controls the value of the constant current of a charge pump driven with a constant current, through an integrator. CONSTITUTION:A phase lock signal 10 of a phase comparator 3 is obtained as a pulse signal whose pulse width is changed in accordance with the lock state of a PLL circuit. This signal is inputted to an integrator 15 through a buffer amplifier 14, and a part of the output of the integrator 15 is inverted by a polarity converting part 16 to obtain a pair of outputs (d) and (e). They are applied as the control input of a current variable charge pump to continuously change the driving current of the current variable charge pump 11, thus changing the loop characteristic of PLL.
申请公布号 JPS6390215(A) 申请公布日期 1988.04.21
申请号 JP19860236466 申请日期 1986.10.03
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIWA MAKOTO
分类号 H03L7/10;H03L7/107;H03L7/18;H03L7/187 主分类号 H03L7/10
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