| 摘要 |
A system clock is produced either from clock signals (t1) recovered in a clock regenerator, based on surface wave filtered technology and having level fluctuations, or from the digital clock signals (t2) internally generated in, for example, an access controller of a ring network, in response to the level of the regenerated clock signals (t1). The change in the source of the system clock is accomplished after an early detection of the level fluctuations, so that the clock signal (t1,t2) currently connected to the clock line are disconnected and, after a short delay time, the other clock signal (t1,t2) is sychronously switched to the clock line. |
