| 摘要 |
PURPOSE:To constitute the delaying circuit without causing an increase of a chip size by a MOS transistor capacity, by providing an inverter element which has connected a gate electrode of a MOS transistor for constituting a capacity element to an input terminal, and also, has connected a source electrode and a drain electrode which have been connected in common, to an output terminal. CONSTITUTION:A gate electrode of a MOS transistor for constituting a capacity element C1 is connected to an input of an inverter I2, and also, a source electrode and a drain electrode which have been connected in common are connected to an output of the inverter I2. In this state, when an input signal is inputted, a signal whose phase is opposite to that of the input signal is transferred to an input A point of the inverter I2 by an inverter I1, and a signal whose phase is opposite to that of the A point is transferred to an input B point of an inverter I3 by the inverter I2. In this case, due to a change/discharge action of the capacity element C1 and a Miller effect, a signal waveform of the A and B points can obtain a rounding delay. A signal which has given a delay to the input signal is outputted from an inverter I4. |
