发明名称 |
COMPLEMENTARY MOS INTEGRATED CIRCUIT |
摘要 |
PURPOSE:To decrease a spike noise at switching by inserting a resistor between the PMOS and the NMOS of an output pre-stage circuit. CONSTITUTION:An analog switch 9 consisting of parallel connection of the PMOS and the NMOS is connected as a resistor between the drain of a PMOS 7 and the drain of an NMOS 8 of the output pre-stage circuit driving an output circuit comprising PMOS 5 and an NMOS 6. Since the through-current at the switching of the output circuit is decreased remarkably, the spike noise caused by the inductance in the circuit is reduced. Moreover, the power consumption is reduced as well. |
申请公布号 |
JPS6388918(A) |
申请公布日期 |
1988.04.20 |
申请号 |
JP19860235047 |
申请日期 |
1986.10.01 |
申请人 |
MITSUBISHI ELECTRIC CORP |
发明人 |
MIYAZAKI YUKIO;OKIDAKA TAKENORI |
分类号 |
H03K19/0948;H03K19/00;H03K19/003;H03K19/094 |
主分类号 |
H03K19/0948 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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