发明名称 |
BINARY ADDER WITH STATIONARY OPERAND AND SERIES-PARALLEL BINARY MULTIPLIER CONTAINING ADDER OF THIS TYPE |
摘要 |
Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.) are wired to incorporate the value of the fixed operand B. The non-fixed operand D is applied in serial form to the control input of a multiplexer. The multiplier also comprises an accumulator-shift register for storing a partial result A of the multiplication. As a function of the state of the multiplexer, the register receives A or A+B. |
申请公布号 |
JPS6389929(A) |
申请公布日期 |
1988.04.20 |
申请号 |
JP19870237080 |
申请日期 |
1987.09.21 |
申请人 |
FURANSHISU JIYUTAN;NIKORA DOUMASHIU;MISHIERU DANA |
发明人 |
FURANSHISU JIYUTAN;NIKORA DOUMASHIU;MISHIERU DANA |
分类号 |
G06F7/501;G06F7/50;G06F7/503;G06F7/506;G06F7/508;G06F7/52;G06F7/527;G06F7/53;G06F7/533 |
主分类号 |
G06F7/501 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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