On-chip bit reordering structure.

摘要

A method and means for transferring bit data from a block of memory data of M bits held in a random access memory chip through an N-bit chip output interface, where M is greater than N, without incurring data gaps when the data is randomly accessed and a wrap protocol is used. In one embodiment, the random access memory chip comprises a random access memory chip, comprises: a chip memory organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data bits in contiguous groups of N bits, where M is greater than N, with each data bit having its own unique address within the blocks, the memory having a predetermined wrap protocol calling for the M bits in a given data block in a prescribed order starting with a designated target bit address; means for randomly addressing a data bit within a given block of data by means of a designated target address; an N bit chip output interface from the memory; chip register means for holding a given block of data, the register having at least M register stages for holding the M data bits of the given data block, wherein the M register stages are grouped into at least a first and a second contiguous groups of N stages each, the register including first gating means for gating the first stage group of N register stages to the N bit output interface, followed in sequence, by the second stage group and higher groups, wherein a bit at one end of a data block is contiguous with a bit at the other end of the data block; and chip steering means for providing in a first set, and in any desired order, the bit at the target address along with N-1 bits having following contiguous addresses for the memory wrap protocol from within the data block to the first group of N register stages, and for providing each successive set of N bits with following contiguous addresses in the wrap protocol to the second and higher register stage groups.