| 摘要 |
PURPOSE:To reduce signal delay time and heighten performance by providing plural computing elements, an output data register, converted data register and plural converters as exclusive logical sum circuit. CONSTITUTION:The bit width of input data 151, 152 and output data register 102 are made to 8 bits, and the interface 154 of data bus to external equipment is set to require parity of 8 bit data and 1 bit. Output bit of a computing element 101B is converted to bit by a converter 103 as an exclusive logical sum circuit and stored in a converted data register 104. Exclusive logical sum of the output of 4 bits of the register 104 is taken by a converter 105 as an exclusive logical sum circuit and converted to 1 bit. Thereby, data 8 bits and parity 1 bit are sent out to the interface 154 with outside. Thus, as it is enough to pass through one step of the circuit 103, reduction of signal delay time becomes possible and performance can be heightened. |
