| 摘要 |
<p>PURPOSE:To prevent clock skewing from occurring, by utilizing a clock personal wiring region to increase a delay time for clock input and shifting timing of the clock signals inputted to several blocks. CONSTITUTION:The same clock signals are inputted to block circuits 1 to 4, and these clock signal wirings are divided into two by buffer circuits 5 and 6. A wiring part 8 for prevention of clock skewing is formed on the output side of the one buffer circuit 5 by utilizing a clock personal wiring region. Length of this wiring part 8 is determined so that the part 8 has wiring capacity large enough to allow the clock signals to be inputted to the block circuits 1 and 2 more slowly than to be inputted to the block circuits 3 and 4. This clock exclusive wiring region is utilized to enlarge the clock input wiring and delay a time for the one-sided clock. Hence, the clock skewing can be prevented from occurring.</p> |
