| 摘要 |
A digital horizontal processor includes a first counter initiated by a horizontal sync pulse for determining a first time interval. When the first counter overflows, it initiates counting in a second counter and in a third counter and initiates a horizontal drive pulse. A feedback pulse is developed at the center of retrace of the video. A latch is coupled between the first and second counters. A reset pulse periodically enables a flip flop to generate, upon occurrence of the feedback pulse, a correction signal to operate the latch to load the count of the second counter into the first counter as a preset. The overall time from horizontal sync to center of retrace is held constant.
|
