| 摘要 |
PURPOSE:To reduce a circuit in scale by changing the bit allocation of a pipeline processing in an adder circuit. CONSTITUTION:Latches 35 and 36 to match the timing of an input signal A and a latch 37 to delay one step of a high order (m) bit, namely, one clock of a reference clock pulse in order to execute the pipeline processing are provided. The latch of latches 49-51 is the same as respective latches 35-37. Next, the output of latches 36 and 50 of an (n) bit is added by an (n) bit adder circuit 38, a carry enters an adder circuit 40 of a high-order (m) bit after one clock is delayed by a latch 39, is added and the result of an (m+n+1) bit is obtained. Next, an LSB is thrown away, an (m+n) bit is obtained, and the then method of the allocation of the bit is a high-order (m+1) bit and a low- oder (n-1). Thus, though the LSB is thrown away and the number of bits is dropped, the result of the high order adder circuit in the pipeline processing may not be dropped to a next step low order adder circuit, and the scale of the circuit becomes smaller. |
