发明名称 DELAY PULSE GENERATING CIRCUIT
摘要 PURPOSE:To easily control the phase difference by providing plural delay pulse generating basic circuits that can set optionally the delay value of an input reference pulse and supplying a delay value selecting signal and an address signal from outside for selection of those basic circuits. CONSTITUTION:An input reference pulse 1 is supplied to the delay pulse generating basic circuits 10i (i = 0-n) via a drive circuit 2. The circuit 10i contains a delay element 4, a selection circuit 5 and a holding circuit 8 and selects one of outputs 4-1 of the element 4. Then addresses are produced 14 by clock signals 17 and 18 and an address clock is selected 12 to supply clock signals 11-19 to the circuit 10i. A selection signal is produced 9 by the signal 17 and supplied to holding circuits 8-24 respectively. The circuits 8-24 receive address clocks 11-19 and deliver a selection signal 7 to select one of delay outputs 4-1 and to obtain pulses 6-22 delayed by the desired value. Thus it is possible to easily control the phase difference between a reference pulse and a delay pulse.
申请公布号 JPS6387015(A) 申请公布日期 1988.04.18
申请号 JP19860232575 申请日期 1986.09.30
申请人 NEC CORP 发明人 ISHIKAWA KENJI
分类号 H03K5/13;H03K5/131 主分类号 H03K5/13
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