| 摘要 |
PURPOSE:To facilitate the extracting of timing signals by providing a delay circuit before a band-pass filter, extracting plural pieces of delay output each of which is delayed by one time slot from one another from the delay circuit, and synthesizing them. CONSTITUTION:By using the delay circuit 2 capable of delaying the signals by one time slot each, the sum of thus delayed outputs of 1-n bits is generated, to obtain an n-fold voltage. In this time, though noise signals are also added together, the summing is noise signals not dependable on the signal is only such that each root value is multiplied by (n). Also, since the noise signal components are distributed uniformly over the entire frequency band, the distinction of them from a timing signal is easy. In case, for instance, of using an 8B1C code, the S/N of a timing signal can be improved by 10log8=9dB. As a result, the requirement with the selection characteristic of the band-pass filter 4 whose central frequency is aligned with that of the timing signal and the requirement for the high gain of an amplifier 5, are mitigated. |
