发明名称 POWER-DOWN/RESET SIGNAL GENERATING CIRCUIT FOR MICROCOMPUTER
摘要 <p>PURPOSE:To prevent the malfunctions of a CPU by applying the power-down signals to the CPU as well as to a single input of a reset signal generating circuit that is backed up by a back-up power supply. CONSTITUTION:A commercial power supply is rectified by a power supply circuit 1 and applied to a CR circuit consisting of a capacitor 2 and a resistance 3. When the voltage of the CR circuit exceeds the sum of value voltage level of a Zener diode 4 and the base-emitter voltage level of a transistor (Tr)5, this Tr5 is turned on and at the same time a TR6 is also turned on. Thus the power-down signal is changed to a high level from a low level. This power- down signal is applied to the clock of an FF7 and a Tr12 is turned on to set the reset signal at a high level. While a CPU starts to monitor the power-down signal when this signal is set at a low level decides a power supply OFF state. The CPU is held when the power supply is cut. In this case, the output of a gate 11 is applied to the reset terminal R of the FF7 and the Tr12 is turned off to set the reset signal at a low level.</p>
申请公布号 JPS6386007(A) 申请公布日期 1988.04.16
申请号 JP19860232876 申请日期 1986.09.30
申请人 FUJITSU GENERAL LTD 发明人 MATSUI AKIHIRO
分类号 G06F1/24;G06F1/00;G06F1/28 主分类号 G06F1/24
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