| 摘要 |
PURPOSE:To diagnose the 0/1 degeneration fault of an output line, and a short-circuited fault between adjacent output lines, by providing a circuit part which connects in parallel serial stages of plural MOS transistors setting the outputs of arbitrary adjacent output lines in an output line array such as an address decoder as inputs. CONSTITUTION:For two arbitrary adjacent output lines in a decoder output line array 1, the serial stage 2 of an NMOS transistor which sets an output as a gate input, and in which two NMOS transistors are connected in series, is provided. One end of each serial stage is connected to a PMOS transistor 3 activated by a pre-charge clock signal phiP through a node 4, and the other end is connected to an NMOS transistor 6 activated by the inverse of phiP through a node 5. It is possible to diagnose the '1' degeneration fault of the decoder output line, and the short-circuited fault between adjacent lines in a CMOS transistor by the output A of the node 4, and the '0' degeneration fault of the decoder output line by the output B of a node 13 In a single fault, it is possible to diagnose the '1' degeneration fault by the output system of the A. As for multiple '1' degeneration fault, the nodes 4 and 5 are always energized when the '1' degeneration fault of the adjacent output lines are generated, and the detection of the fault is possible, but it is impossible to specify the fault. Also, a case that it is impossible to diagnose the fault at a part in the neighborhood of both ends of the decoder output line, may happen, but in an ordinary case, no double fault diagnosis can be performed, therefore, it is enough to diagnose the double fault. |
