| 摘要 |
A circuit delays a digital signal by means of shift registers. The digital signal is first stored at a high clock frequency (CK1) in an intermediate memory (21), after which it is alternately stored in intermediate memories (L2, L3) by means of half-clock frequency (CK1/2) synchronisation signals, displaced by a half-clock period. The outputs of these memories (L2, L3) are each connected to the inputs of a shift register (FIFO1, FIFO2). The signals, after a predefinable time, are again extracted by reading cycles (CKR1, CKR2) and each fed to an intermediate memory (L4, L5) which is also read at a clock frequency (CK1/2). The intermediate memory outputs (L4, L5) are connected to the inputs of a multiplex (MUX) circuit, which again reverses the initially-effected breakdown of the signals into two signal channels, and again inserts the signal in the correct sequence.
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