| 摘要 |
<p>PURPOSE:To improve the utilization of the area of a semiconductor chip, and to scale down the size of the chip by fractionating and forming the size of a fundamental cell constituting a peripheral circuit section to small sections in the same manner as a fundamental cell organizing an internal circuit section and using an arbitrary number of the fundamental cells. CONSTITUTION:An internal circuit section 2 is constituted arbitrarily of a large number of fundamental cells 21, to each of which predetermined circuit elements are shaped. The internal circuit sec tion 2 can have an optional logic circuit function by determining only wiring patterns in the fundamental cells and among the fundamental cells in response to order specifications from users. A peripheral circuit section 3 is positioned among the internal circuit section 2 and terminal pads 4. The peripheral circuit section 3 has a large number of fundamental cells 51, 52 in the same manner as the internal circuit section 2. A large number of the fundamental cells 51, 52 formed to the peripheral circuit section 3 are each disposed under the state in which two kinds of the fundamental cell 51 for an input buffer and the fundamental cell 52 for an output buffer are paired.</p> |
