| 摘要 |
PURPOSE:To increase breakdown strength without particularly augmenting a process by forming a p layer for preventing field concentration at the same time as the formation of a channel stopper p layer in the periphery of an n channel MOSFET along the periphery of a p layer as a base in an npn transistor. CONSTITUTION:Since a p layer 12 is shaped along the peripheral section of a base-collector junction in a bipolar npn transistor, curvature in the surface section of a base junction is enlarged, field concentration is removed, and the breakdown strength of a bipolar section can be improved sharply to 100V from 40V under an actual condition. Consequently, a bipolar-CMOS process can be applied up to a product at 100V service voltage. Since the p layer 12 in the peripheral section of a bipolar element is shaped at the same time as the formation of a channel stopper p layer 13 in the periphery of a p well in a CMOSFET, the formation of the p layer 12 can be realized only by changing one part of a mask pattern in a conventional process. Accordingly, the effect of the reduction of cost is displayed without complicating the process as the manufacture of a semiconductor device. |
