| 摘要 |
PURPOSE:To attain higher integration through reducing the width of a separating region and to juxtapose a high tension withstanding element separated by an insulating film by a method wherein a first MIS field effect transistor is formed on a buried, re-crystallized silicon substrate and a second MIS field effect transistor is formed on a semiconductor substrate. CONSTITUTION:In a NAND-gate ROM, bit line BL1, BL3, BL5, BL7 constituted of first MOSFETs lined up on the surfaces of buried, re-crystallized Si substrates 6a-6d, and bit lines BL2, BL4, BL6, constituted of second MOSFETs lined up on belt-geometry surface regions 8a-8c of an Si substrate, are arranged alternately. Neighboring bit lines are separated from each other by an isolating SiO2 insulating film 5 that separates the buried, re-crystallized Si substrates 6a-6d from each other. Accordingly, a separating region between bit lines may be formed very small in width, which greatly enhances the degree of integration. Further, a high tension withstanding element capable of handling a high driving pressure may be package together with an ordinary element and, further, latch-up may be prevented in a high-integration CMOS circuit. |
