| 发明名称 |
Circuit arrangement for reducing the settling time of logarithmic amplifiers |
| 摘要 |
A circuit arrangement for reducing the settling time of amplifiers to which photoelectronic components are connected. A control circuit is provided which, operating in conjunction with components of this circuit arrangement, prevents the parasitic capacitance of the photoelectronic component from being charged up when the circuit arrangement is connected to the operating voltage.
|
| 申请公布号 |
US4737668(A) |
申请公布日期 |
1988.04.12 |
| 申请号 |
US19860911862 |
申请日期 |
1986.09.26 |
| 申请人 |
ERNST LEITZ WETZLAR GMBH |
发明人 |
BLETZ, WALTER;MAGEL, ROLF;BILL, HELMUT |
| 分类号 |
H03G11/08;G01J1/44;G03B7/081;G06E3/00;G06G7/24;H03F1/30;H03F3/08;H03G3/20;(IPC1-7):H03K5/00;H03K3/42;H03K17/56 |
主分类号 |
H03G11/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
