发明名称 INTEGRATED CLAMPING CIRCUIT
摘要 PURPOSE:To limit a clamp level with optional width by supplying a clamp potential as collector potentials of respective transistors (TR) which form a differential amplifier. CONSTITUTION:In regard to the collector voltage of a TR 2 which is determined by TRs 1 and 2, a load resistance 6, and a constant current source 12, a TR 28 sets the lower-limit level of the collector point level of the TR 2 in the absence of a signal input, and a TR 29 sets the upper-limit level. Then the upper-limit and lower-limit clamp potential levels are varied at the same rate to the collector-point bias potential in the absence of a signal input optionally with a control voltage inputted from a terminal 40 by the differential amplifier consisting of TRs 20 and 21, load resistances 37 and 38, emitter resistances 35 and 36, and a constant current source 31.
申请公布号 JPS6380610(A) 申请公布日期 1988.04.11
申请号 JP19860226799 申请日期 1986.09.24
申请人 NEC CORP 发明人 KUWAJIMA TAKESHI
分类号 H03G11/00;H03G11/02 主分类号 H03G11/00
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