| 摘要 |
PURPOSE:To attain high-speed DMA transfer by applying DMA transfer in interlocking with an address register and a transfer word register when a DMA transfer request is inputted to a DMA control circuit and applying transfer from a memory to a bus when the transfer is finished. CONSTITUTION:A central processing unit on the bus 1 side completes data setting to each register of counters 5, 9, 6, 8. When the DMA transfer request from the bus 1 to the bus 37 and the DMA transfer request from the bus 37 to the bus 1 take place simultaneously, the DMA transfer request generated from the bus 1 is inputted to the DMAC 19 and the DMA transfer request generated from the bus 37 is inputted to the DMAC 24. The DMAC 19 is interlocked with the counters 5, 6 to apply DMA transfer from the bus 19 to the DPM 32 and the DMAC 24 applies DMA transfer from the bus 37 to the DPM 33 in interlocking with the counters 9, 8. When each transfer is finished, the DMAC 24 applies DMA transfer from the DPM 32 to the bus 37 in interlocking with the counters 9, 8, and the DMAC 19 applied DMA transfer from the DPM 33 to the bus 1 in interlocking with the counters 5, 6. |
