发明名称 |
NOISE REDUCTION CIRCUIT FOR A VIDEO SIGNAL |
摘要 |
The invention is concerned with the processing circuit of image signal which can reduce a correlation error and improve S/N ratio. The image signal (a) in terminal (1) is supplied to adder (2) and simultaneously delayed in 1H delay-circuit (3). The delayed image signal (b) and the image signal (a) is supplied to the subtractor (4) . As a result, the signal (d) which is supplied to a noise-clip circuit (5) is formed. The noise-clip circuit extracts only a correlation error signal and the signal (e) is formed. The signal (e) and the output signal (c) of an adder (2) is supplied to the adder (6). Therefore, in the final signal the noise and S/N ratio are improved.
|
申请公布号 |
KR880000529(B1) |
申请公布日期 |
1988.04.09 |
申请号 |
KR19840001729 |
申请日期 |
1984.04.02 |
申请人 |
NIPPON VICTOR CO.,LTD. |
发明人 |
NAKAGAKI, SHINTARO;NEGISHI, ICHIRO |
分类号 |
H04N5/21;(IPC1-7):H04N5/21 |
主分类号 |
H04N5/21 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|