发明名称 LSI FOR PROCESSING PARALLEL IMAGE
摘要 <p>PURPOSE:To minimize an image data input output port by processing the local image data of 4X4 picture elements with a basic module having four processor elements for a parallel image processor. CONSTITUTION:To a parallel image processing processor 1, one column part f14-f44 of the local image data is given in parallel from an image memory 2 and the arithmetic result is stored into the image memory 2. Input image data f14 is inputted through a shift register 10 to a processor element 11, and image data f14 of the processing object from the shift register 10 and load data W14 from a load memory 12 are given and multiplied. The result is given to an arithmetic circuit 13, and the arithmetic result of four processor elements 11 is added and inputted to an arithmetic circuit 14. To the arithmetic circuit, arithmetic data from the parallel image processing processor 1 of the front step inputted from an arithmetic result input port 16 are also inputted, these are added and outputted to a next basic module. Thus, the four steps of basic modules 9A-9D are overlapped and g=SIGMAfijwij is obtained from a final step 9D.</p>
申请公布号 JPS6379180(A) 申请公布日期 1988.04.09
申请号 JP19870050051 申请日期 1987.03.06
申请人 HITACHI LTD 发明人 KOBAYASHI YOSHIKI;FUKUSHIMA TADASHI;OKUYAMA YOSHIYUKI
分类号 G06F15/16;G06F15/80;G06T1/20;G06T5/20;H04N19/00;H04N19/42;H04N19/436 主分类号 G06F15/16
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