发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To perform the sum total calculation of a 1st or 2nd operands only by using a 1st and 2nd selection circuits in addition to an arithmetic frequency identifying circuit which identifies a 1st time or 2nd times in a sum total calculation mode of either one of both operands only. CONSTITUTION:When an instruction for sum total calculation of the 1st operand Ai only is stored in an instruction register 3, the output signal lines 110 and 111 of an arithmetic frequency identifying circuit 8 output logics 0 and 1 respectively in a 1st arithmetic mode. A selection circuit 6 selects a signal line 100 and delivers the operand Ai read out of a vector register 1 to a signal line 112. While a selection circuit 7 selects the logic 0 and outputs it to a signal line 113. An adder circuit 5 adds both data together and the result of this addition is stored in the register 1. In a 2nd arithmetic mode both lines 110 and 111 are set at logic 0 and circuits 6 and 7 outputs the 1st and 2nd operands of the register 1 respectively.
申请公布号 JPS6379172(A) 申请公布日期 1988.04.09
申请号 JP19860223764 申请日期 1986.09.24
申请人 NEC CORP 发明人 SODA YOSHIHISA
分类号 G06F17/16;G06F7/50;G06F7/509 主分类号 G06F17/16
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