| 摘要 |
<p>PURPOSE:To contrive to reduce a delay time by loading and inputting an output of a FF changed directly by a clock at out of synchronism in a frame synchronizing circuit, holding it and hunting to eliminate the need for a gate between the FF and a frame counter. CONSTITUTION:When an output of a synchronizing protection circuit is logical 1 in the normal state and out of synchronism takes place in a code error of a transmission line, an output of a frame pattern detection circuit is deviated from the normal position. However, the output of a 3-input NOR gate 15 is always zero independently of the frame pattern detection signal. Thus, when a value of a frame counter 10 is N-2, the output of a decoder 12, a 2-input NOR gate 13 and a d-FF 14 is changed in each timing and the Q output of the b-FF 14 goes to '0'. Thus, the counter 10 loads '0' and acts like an N-adic counter. That is, the synchronizing protection is applied and even if pattern dissidence is detected, it is not decided as out of synchronism and the operation of synchronizing restoration at the forward protection state is held.</p> |
