| 摘要 |
<p>PURPOSE:To simplify the configuration of circuit by letting a data speed conversion function and a clock re-reading function have one buffer section. CONSTITUTION:The buffer circuit is provided with a buffer section 11 having a data speed conversion function and a clock re-read function, an output clock generating section 10, a read address counter 9, a write address counter 4, a thinning-out control section 3, and a frame synchronization section 2. The output clock generating section 10 generates an output clock S11. The write address counter 4 is operated by an input clock S2 to generate a write address signal S5 for the buffer section 11. The read address counter 9 is operated by the output clock S11 to generate a read address signal S10. A frame synchronization section 2 establishes frame synchronization by a unique word included in an input data string S1. The thinning-out control section 3 generates an address interleave signal S4 to the write address counter 4 by using a frame synchronizing signal S3.</p> |
