发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To easily extract a chip including a bit having a narrow action allowance by changing the internal voltage of a discharging circuit forcibly from an external part at the time of non-selection, preventing a discharging current from conducting, changing forcibly the internal potential of an information holding current generating circuit from the external part, decreasing an information holding current to execute a functional test. CONSTITUTION:At the time of the functional test, a current operating as a holding current, for example, a discharging current is controlled from an external part and decreased. Namely, it is realized by driving a terminal 13 for supplying the source voltage of an internal power source circuit 12 by the voltage lower than the terminal 7 of other circuit. This can easily add DELTAVEE (forward direction voltage of transistor) by providing respectively independently a power source terminal 7 and terminals 6 and 13 on a chip, connecting the 6 and 13, separating from the terminal 7, providing them and connecting them to the same terminal at the time of loading to a package. Thus, at the time of the functional test, the action allowance of a memory cell can be measured while the holding current is decreased, therefore, the detection of the memory cell having the narrow action allowance can be easily executed.
申请公布号 JPS6376200(A) 申请公布日期 1988.04.06
申请号 JP19860219549 申请日期 1986.09.19
申请人 HITACHI LTD 发明人 YAMAGUCHI KUNIHIKO;HONMA NORIYUKI;KANETANI KAZUO;NANBU HIROAKI
分类号 G11C11/413;G11C29/00;G11C29/50;H01L27/10 主分类号 G11C11/413
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