| 摘要 |
PURPOSE:To shorten waiting time by controlling a RAM time-division-wise by using a basic signal from a basic signal generation circuit and a read/write signal and a chip selecting signal from two CPUs. CONSTITUTION:The common RAM 13 is controlled time-division-wise alternately by the two CPUs 11, 12. Latch circuits 14, 20 to latch respective address data are inserted in the address buses of the CPUs 11, 12 and the RAM 13, and in their data buses, latch circuits 15, 19, 21, 25 to latch respective write data and read data. The basic signal generation circuit 26 generates a basic signal to let the respective CPUs 11, 12 alternately control the RAM 13 time-division- wise. A control signal generation circuit 27 generates a read/write control signal in accordance with the said basic signal and the read/write signal and the chip selecting signal from the respective CPUs 11, 12 so that the respective CPUs 11, 12 will alternately control the RAM 13 time-division-wise. |
