DATA TRANSMISSION APPARATUS FOR A MULTIPROCESSOR SYSTEM

摘要

The appts. has memory units, a number of processors, a common bus, an address bus, a data bus, an answer bus connected between the memory unit and processors, and a bus control unit for controlling data transfer. The appts. includes separate bus request control lines associated with the address bus, data bus and answer bus and connected to the memory unit and processors. The bus control unit is connected to these control lines to control bus selection by a bus requesting unit and/or processor for each bus in response to a bus request signal.