| 摘要 |
PURPOSE:To easily analyze error information by interrupting clock stopping operation at the time of generating an error during the execution of a normal program, and at the time of reproducing the error, executing the clock stopping operation. CONSTITUTION:Since an AND circuit 14 interrupts the setting of a JK flip flop (FF)4 at the time of an error during the execution of the normal program, clock supply is not stopped and error processing based upon an error processing program is enabled. When the program executed at the time of generating the error is executed after setting up a JK FF13 and the JK FF4 is set up by an error signal passed through an AND circuit 14, a clock to be supplied to scanning FFs 7-9 is stopped. At the time of stopping the clock, the scanning FFs 7-9 inputs scan-in signal from an SI terminal to hold data obtained at the time of generating the error and output scan-out signal to an SO terminal, so that the signal is compared with the error processed result and the contents of the fault can be inspected. Thus, the fault analyzing time can be shortened. |
