MOS logic input circuit having compensation for fluctuations in the supply voltage

摘要

A CMOS logic circuit includes a first MOS transistor of one conductivity type and second and third MOS transistors of a conductivity type opposite to that of the first MOS transistor, the first to third MOS transistors being conducted in series with each other between first and second power source terminals. The gate of the first MOS transistor and the gate of one of the second and third MOS transistors commonly receive a input signal. The gate of the other of the second and third MOS transistors, serving as a correcting transistor, is connected to the first power source terminal. A series connecting point of the first and second MOS transistors serves as an output node. A channel size ratio W/L (where W is the channel width and L is the channel length) or an absolute value of a gate threshold voltage of the first MOS transistor is different from that of the correcting transistor.