| 摘要 |
A process for forming a silicon-on-sapphire integrated circuit comprises forming a layer of a conformal dielectric material, such as silicon dioxide, over a sapphire substrate having at least one island of silicon on a major surface thereof; forming a layer of a planarizing material over the dielectric layer, anisotropically etching the planarizing material for a time sufficient to expose the surface of the dielectric layer overlying the island; etching the dielectric layer for a time sufficient to expose at least the top surface of the island; removing the remaining planarizing material, growing a thin layer of gate oxide on the exposed surface of the island and providing a patterned layer of conductive polycrystalline silicon thereover. The etching of the dielectric layer can be continued to at least partially expose the sidewall surface of the islands. Preferably, etching is continued for a time sufficient to completely expose the sidewall surfaces of the islands and a portion of the surface adjacent thereto. A separate MOSFET is formed on each island and includes source and drain regions spaced by a channel region and a channel dielectric over the channel region.
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