发明名称 SYSTEM FOR TESTING ADDRESS BUS
摘要 PURPOSE:To easily test all address busses by setting plural address spaces to be tested and successively allocating these address spaces on memory cards which can be arbitrarily allocated on a physical address space. CONSTITUTION:A memory card 5 which can be allocated on an optional space of the physical address space consists of a comparing part 6 which selects the memory card 5 if 8-bit data set to an address register 7 which designates upper eight bits of an address bus and address data of upper eight bits outputted to an address bus 100 coincide with each other as the result of comparison, an address decoder 8 which selects a memory element, a memory part 9, etc. Nine address spaces are set as the test object address space, which tests the address bus 100, so that respective bits of the address bus are turned on/off, and address busses B0-B19 are verified in an address space 1, and address busses B20-B27 are verified in address spaces 2-9. Thus, all address busses are easily tested.
申请公布号 JPS6371750(A) 申请公布日期 1988.04.01
申请号 JP19860216450 申请日期 1986.09.12
申请人 FUJITSU LTD 发明人 NIIYAMA YUKICHI;YAMADA SHINJI
分类号 G06F11/22;G06F12/16;G06F13/00 主分类号 G06F11/22
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