发明名称 OPERATION PROCESSING DEVICE
摘要 PURPOSE:To considerably reduce the number of partial products and to contrive to increase the operation speed of an operation processing device by providing two kinds of multiplier recording method and adding a circuit for subtraction. CONSTITUTION:A multiplier recording circuit 11 records a multiplier to a digit number with 4-notation sign where each digit is -2, -1, 0, 1, or 2, and an intermediate partial product generator 110 generates an intermediate partial product. A redundancy subtractor 120 subtracts the partial product generated by an adjacent odd intermediate partial product generator 110 from that generated by the intermediate partial product generator 110 and outputs the difference as a redundant binary number where each digit is -1, 0, or 1. A redundancy adder 130 adds general redundant binary numbers in the redundant binary system, and a redundant binary-binary converter 140 converts the redundant binary number obtained as the product to a binary number.
申请公布号 JPS6371729(A) 申请公布日期 1988.04.01
申请号 JP19860216592 申请日期 1986.09.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHIYAMA TAMOTSU;KUNINOBU SHIGERO
分类号 G06F7/533;G06F7/49;G06F7/52 主分类号 G06F7/533
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