发明名称 SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To remarkably reduce waveform distortion of an output signal by feeding back a DC component of an output signal of a delay element receiving an FM signal negatively to an input bias voltage of the delay element so as to control the input bias voltage. CONSTITUTION:The FM signal inputted from the input terminal 1 receives a prescribed bias by resistors R1, R2 and is inputted to a delay element 2. The delay element 2 consists of series connection of, e.g., many C-MOS gates 6. Then the DC component is obtained from the input signal and the output signal of opposite polarity by using a resistor R4 and a capacitor C2 and fed back negatively to the input bias voltage via the resistor R3. When the input signal and the output signal of the delay element 2 are of the same polarity, an inverting circuit is inserted between the resistors R4 and R3. Thus, the waveform distortion in the output signal is reduced remarkably. The circuit is suitable for the signal processing system of a VTR.
申请公布号 JPS6372216(A) 申请公布日期 1988.04.01
申请号 JP19860216580 申请日期 1986.09.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HONJO MASAHIRO;TAKEUCHI AKIHIRO
分类号 H03K5/08;H03K5/007;H03K5/04;H04N5/14;H04N5/91 主分类号 H03K5/08
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