| 摘要 |
The output of a timing element (ZG), receiving a timing signal (ZT), is connected to the setting input of a bistable time-detecting flip-flop (ZEK), the output of which is connected to the input of an access-detecting flip-flop (ZUK). On the output side, the access-detecting flip-flop (ZUK) is connected both to the input of the microprocessor (MP) intended for the waiting signal (WAIT), and to the first input of a first OR element (OG1). The second input of the first OR element (OGI) is connected to an output of the microprocessor (MP) receiving a memory enabling signal (SRW); on the output side, it is connected to the input of the event flip-flop (EK). The output of the event flip-flop (EK) is connected as a starting signal (START) to a change-over input (UM) of a controller logic (AL) of a dynamic random-access memory (DSLS) and to the first input of a second OR element (OG2), which on the output side is connected to an enabling input (EN) of a clocked sequence control (ABL). The negated output of the time-detecting flip-flop (ZEK) is connected to the first input of an AND element (UG), the output of which is connected to a resetting input (RS) of the clocked sequence control (ABL). <IMAGE>
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