发明名称 MOS LOGIC INTEGRATED CIRCUIT
摘要 PURPOSE:To inhibit the hot carrier phenomenon of a fine MOS transistor and a logic circuit, etc. using the MOS transistor by increasing one N-channel MOS transistor to one logic transistor. CONSTITUTION:When an input signal to an input terminal 4 is a high level signal, a transistor 1 is turned ON, and a gate for a MOS transistor 2 is connected to a power supply VDD and the transistor 2 is turned ON at all times, thus outputting a low level signal to an output terminal 5. When the input signal to the input terminal 4 is a low level signal, inversely, the MOS transistor 1 is turned OFF, and a MOS transistor 31 is turned ON at all times, thus outputting a high level signal to the output terminal 5. When the N-channel MOS transistor 1 is turned OFF, the drain voltage VD1 of the transistor 1 is made lower than supply voltage VDD only by the threshold voltage Vth of the MOS transistor 2, thus inhibiting a hot carrier phenomenon. However, an output level at that time is brought to a level equal to approximately supply voltage VDD.
申请公布号 JPS6370575(A) 申请公布日期 1988.03.30
申请号 JP19860213957 申请日期 1986.09.12
申请人 SONY CORP 发明人 YAMADA TAKAAKI;NAKASHIO MIAKI
分类号 H01L21/8234;H01L27/088;H01L29/78 主分类号 H01L21/8234
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