发明名称 Process for manufacturing semiconductor memory device
摘要 A dynamic RAM having a memory cell constituted by a capacitor element, utilizing a trench or moat formed in a semiconductor substrate, and a MISFET. One of the electrodes of the capacitor element is connected to the MISFET constituting part of the memory cell at the side wall of the upper end of the moat for forming the capacitor element. This electrode is connected in self alignment with a semiconductor region which serves as either the source or drain of the MISFET.
申请公布号 US4734384(A) 申请公布日期 1988.03.29
申请号 US19860862638 申请日期 1986.05.13
申请人 HITACHI, LTD. 发明人 TSUCHIYA, OSAMU
分类号 H01L27/10;H01L21/8242;H01L27/108;(IPC1-7):H01L21/76;H01L21/82 主分类号 H01L27/10
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