Dynamic random access memory arrangements having WE, RAS, and CAS derived from a single system clock

摘要

A dynamic random access memory arrangement for storing digital television signal data under control of a system clock signal CK and input address signals A0 to A17 associated with the data, has a dynamic random access memory having a data input and a data output for the data, and an address input for the input address signals, the dynamic random access memory being controlled by a write enable signal &upbar& W, a row address strobe signal &upbar& R and a column address strobe signal &upbar& C, and a logic circuit is provided to derive the signals &upbar& W, &upbar& R and &upbar& C from the system clock signal CK with respective timings each determined by a leading edge of a pulse of the system clock signal CK and delay devices.